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The semiconductor manufacturing
environment is unique and extremely complex. The process typically
consists of four main sub-processes/stages [Uzsoy et al. 1992]:
- Wafer
fabrication
- Wafer probe
- Wafer assembly
- Wafer testing
In the wafer fabrications stage, the basic
integrated circuit (IC) is built up layer by layer by going through
complex processing steps such as photolithography, etching and
diffusion in factories known as wafer fabs. The wafer fabrication stage
is the most complex stage of production, typically consisting of 300 to
500 process steps which are performed by complex tool-groups. Each of
the mix of products has its own process flow with a certain number of
steps in the flow. In wafer probe, the newly manufactured circuits are
tested for basic functionality and the functioning IC’s are
sent ahead to the wafer assembly stage where they are packaged. In the
final step, the packaged IC’s are tested for quality and
reliability before being sent to the customer. Figure 1, is a step-wise
representation of the wafer fabrication stage.
The problem of developing an optimal
production schedule in the horizon of a week to a day for a
semiconductor manufacturing system is an extremely hard problem due to:
- Large number of process steps for each
wafer
- Stochastic nature of the yields and process
- Re-entrant flows
- Large number of jobs
- Large number of machines / tools
- Sequence dependent changeover times
Optessa
MLS is offered in a special configuration, called Optessa MLS-SC, for
semiconductor manufacturing scheduling. The system uses modern
stochastic search techniques to rapidly find a near optimal solution,
even for large problems.
Optessa provides the most advanced
manufacturing sequencing and scheduling software available today. It
has been deployed by some of the world’s largest and most
innovative manufacturers.
Optessa MLS-SC can
generate a schedule that optimizes a cost function, after considering
all rules and constraints. The computational engine at the core of Optessa MLS-SC
optimizes the entire solution by a multi-pass iterative process
involving millions of evaluations. This is a superior approach to
simple dispatching heuristics, one pass schemes or those based on
classical OR techniques. The result will be a high quality schedule
that maximizes resource utilizations, minimizes changeovers and delays,
and reduces costs. The user will not be required to spend several hours
manually adjusting the generated sequence, as is the case with
suboptimal solution techniques.
Optessa MLS-SC
considers the following requirements/complexities in semiconductor
manufacturing scheduling:
- Rescheduling
- Re-entrant Flows
- Non Uniform Load
- Setup Times
- Downtimes
- Rework
- Rejection of Lots
- Hot Lots
- Matching of Tools
- Auxiliary Resources
- Test/Monitor Wafers
- Send Ahead Wafers
- Trial Lots
- Processing Time-Windows
- Utilization of resources
- Integration with MES
- Manual Overrides
- Rules/Constraints for Scheduling
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